Field effect transistor device spacers

ABSTRACT

A method for forming field effect transistors comprises forming a first dummy gate stack over a first fin, forming a second dummy gate stack over a second fin, depositing a first layer of spacer material on the first dummy gate stack, the first fin, the second dummy gate stack, and the second fin, patterning a first masking layer on the first dummy gate stack and the first fin, etching to remove portions of the first layer of spacer material and form a spacer adjacent to the second dummy gate stack, removing the first masking layer, epitaxially growing a silicon material on the second fin, depositing a layer of oxide material on the first layer of spacer material, the first epitaxial material and the second dummy gate stack, and depositing a second layer of spacer material on the layer of oxide material.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of and claims priority from U.S. patent application Ser. No. 14/817,504, filed on Aug. 4, 2015, entitled “FIELD EFFECT TRANSISTOR DEVICE SPACERS”, the entire contents of which are incorporated herein by reference.

BACKGROUND

The present invention relates to field effect transistors (FET), and more specifically, to finFET devices.

FinFET devices typically include semiconductor fins that are arranged on a substrate. Gate stacks are arranged on the fins and define channel regions of the device. The source and drain active regions of the device are adjacent to the channel region.

In fabrication, sacrificial dummy gate stacks are often formed prior to forming the active regions of the device. The dummy gate stacks define the channel region, and are formed from a material such as polysilicon. A material such as nitride or oxide is often used to form spacers adjacent to the gate stacks. The dummy gate stacks allow fabrication processes such as ion implantation and annealing or epitaxial growth process to be performed prior to forming the gate stacks. Such high temperature processes can undesirably degrade the materials in the gate stacks, thus the dummy gate is used to define and protect the channel region while the active regions are formed.

Often a wafer includes nFET and pFET devices. The devices are distinguished by the type of materials in the active regions of the devices. The active regions may be formed by ion implantation and/or epitaxially growing doped silicon materials.

SUMMARY

According to one embodiment of the present invention, a method for forming field effect transistors comprises forming a first dummy gate stack over a first fin, forming a second dummy gate stack over a second fin, depositing a first layer of spacer material on the first dummy gate stack, the first fin, the second dummy gate stack, and the second fin, patterning a first masking layer on the first dummy gate stack and the first fin, etching to remove portions of the first layer of spacer material and form a spacer adjacent to the second dummy gate stack, removing the first masking layer, epitaxially growing a silicon material on the second fin, depositing a layer of oxide material on the first layer of spacer material, the first epitaxial material and the second dummy gate stack, and depositing a second layer of spacer material on the layer of oxide material.

According to another embodiment of the present invention, a method for forming spacers of a field effect transistor comprises patterning a first fin, forming a first dummy gate stack on the first fin, forming a first layer of spacer material on the first fin and the first dummy gate stack, removing portions of the first layer of spacer material to define a spacer adjacent to the first dummy gate stack, epitaxially growing a silicon material on exposed portions of the first fin, forming a layer of oxide material on the silicon material, the spacer, and the dummy gate stack, and forming a second layer of spacer material on the oxide layer.

According to yet another embodiment of the present invention, a field effect transistor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin is doped with n-type dopants, a second semiconductor fin arranged on the substrate, the second semiconductor fin is doped with p-type dopants, a first gate stack arranged over the first semiconductor fin, a second gate stack arranged over the second semiconductor fin, a first spacer arranged adjacent to the first gate stack, the first spacer having a substantially uniform thickness, and a second spacer arranged adjacent to the second gate stack, the second spacer having a substantially uniform thickness, wherein the thickness of the first spacer is substantially similar to the thickness of the second spacer.

Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 illustrates a cross sectional view of a two finFET devices.

FIG. 2 illustrates a side cut-away view of fins formed on a substrate.

FIG. 3 illustrates the resultant structure following the patterning and deposition of a masking layer.

FIG. 4 illustrates the resultant structure following the removal of the masking layer and an epitaxial growth process.

FIG. 5 illustrates the deposition of an oxide layer.

FIG. 6 illustrates the deposition of a second layer of spacer material.

FIG. 7 illustrates the patterning of a mask layer.

FIG. 8 illustrates the resultant structure following an etching process.

FIG. 9 illustrates the resultant structure following an etching process.

FIG. 10 illustrates the formation of spacers.

FIG. 11 illustrates the formation of source and drain regions.

FIG. 12 illustrates the patterning of a masking layer.

FIG. 13 illustrates the removal of the masking layer.

FIG. 14 illustrates the resultant structure following the deposition of an insulating layer.

FIG. 15 illustrates the resultant structure after a planarizing process.

DETAILED DESCRIPTION

The formation of nFET and pFET devices on a single wafer often includes forming the active regions of the nFET devices and the pFET devices in separate fabrication steps to allow the formation of active regions having different types of dopant materials. For example, when the active regions of the nFET devices are being formed, the pFET devices are protected by a layer of material that prevents exposure of the pFET to the nFET active region fabrication process. Likewise, when the active regions of the pFET devices are being fabricated, the nFET devices are protected to prevent contamination of the nFET devices. This process often results in asymmetric pFET and nFET spacers that affect the performance of the devices. The embodiments described below provide for symmetrical spacers in pFET and nFET devices formed on a substrate.

FIG. 1 illustrates a cross sectional view of two finFET devices having fins 102 a and 102 b and dummy gate stacks 104 a and 104 b. A layer of spacer material 106 a and 106 b is deposited over the devices and formed into spacers. A second layer of spacer material 108 is formed over the devices. In the illustrated example, the active region of the fin 102 b has been formed by an epitaxial growth that was performed prior to the deposition of the second layer of spacer material 108, while the spacer 108 a was formed prior to the epitaxial growth on the fin 102 a. The resulting structure includes finFET devices having asymmetrical spacers 108 where the spacer material 108 at the base of the gate stack 104 a in region 101 a has a greater thickness than the spacer material at the base of the gate stack 104 b in region 101 b. When NFET and PFET have different spacer thickness (asymmetrical spacers), forming balanced junctions for good device behavior becomes difficult. Unbalanced junctions may either cause higher external resistance or may short channel control. The thickness of the spacers also affects the contact area, and thus, it is desirable to minimize the spacer thickness.

FIGS. 2-15 illustrate an exemplary method of forming symmetrical spacers for nFET and pFET fin FET devices on a wafer. FIG. 2 illustrates a side cut-away view of fins 204 a and 204 b are formed on a substrate 202 using, for example, a photolithographic patterning and etching method such as reactive ion etching (ME). Dummy gate stacks 206 a and 206 b are arranged on the fins 204 a and 204 b respectively. The dummy gate stacks 206 are formed by for example, depositing a layer of polysilicon material or oxide material 208 and an oxide or nitride material 210 over the layer of polysilicon material 208. The photolithographic patterning and etching process may be used to pattern the dummy gate stacks 206. Following the patterning of the dummy gate stacks 206, a layer of spacer material 212 is deposited over the exposed surfaces. In the illustrated embodiment, the spacer material 212 includes a low-k material such as, for example, SiN, SiBCN, SiOCN, or SiOC that may be deposited by, for example, a chemical vapor deposition (CVD) process.

FIG. 3 illustrates the resultant structure following the patterning and deposition of a masking layer 302 over the dummy gate stack 206 a and fin 204 a. The masking layer may include, for example, an organic material. After the masking layer 302 is patterned, an anisotropic etching process such as, for example, RIE is performed to form the spacers 304 adjacent to the dummy gate stack 206 b. The etching process removes a portion of the spacer material 212 to expose portions of the fin 204 b.

FIG. 4 illustrates the resultant structure following the removal of the masking layer 302 (of FIG. 3) and an epitaxial growth process. The masking layer may be removed by, for example, a plasma ashing process. The epitaxial growth process grows an epitaxial material, such as, for example, silicon or silicon germanium on exposed silicon surfaces of the fin 204 b to further define source and drain regions (active regions) 402. The layer of spacer material 212 over the dummy gate stack 206 a and the fins 204 a protects the silicon material of the fin 204 a from seeding the epitaxy. In some embodiments, the epitaxially grown material in the active regions 402 may be in-situ doped with either n-type dopants or p-type dopants during the epitaxial growth process.

FIG. 5 illustrates the deposition of an oxide layer 502 over the exposed portions of the spacer material layer 212, the spacers 304, the active regions 402, and the dummy gate stacks 206. The oxide layer 502 is relatively thin approximately 1 to 5 nanometers. The oxide layer 502 is formed using, for example a CVD process.

FIG. 6 illustrates the deposition of a second layer of spacer material 602 over the oxide layer 502. The second layer of spacer material 602 may include, for example, a nitride material that is deposited by a CVD process.

FIG. 7 illustrates the patterning of a mask layer 702. The masking layer 702 may be formed by, for example, a lithographic deposition and patterning process. The mask layer 702 is patterned over the second layer of spacer material 602 on the dummy gate stack 206 b, and the active regions 402.

FIG. 8 illustrates the resultant structure following an etching process such as, for example, a chemical wet etching process or a reactive ion etching process that removes the exposed portions of the second layer of spacer material 602. The etching process is selective to the material in the oxide layer 502 such that the oxide layer 502 is exposed, but not substantially etched.

FIG. 9 illustrates the resultant structure following an etching process such as, for example, a diluted hydrofluoric (HF) or a buffered HF etching process. That removes the exposed portions of the oxide layer 502. The removal of the exposed portions of the oxide layer 502 exposes a portion of the spacer material layer 212 over the dummy gate stack 602 a and the fin 204 a.

FIG. 10 illustrates the formation of spacers 1002 adjacent to the dummy gate stack 206 a. The spacers 1002 are formed by an anisotropic etching process such as, for example, RIE that removes the exposed horizontal surfaces of the layer of spacer material layer 212 (of FIG. 9).

FIG. 11 illustrates the formation of source and drain regions (active regions) 1102 using, for example, an epitaxial growth process that grows a silicon material on the exposed portions of the fin 204 a. The source and drain regions 1102 may be in-situ doped during the epitaxial growth process with n-type or p-type dopants. In the illustrated embodiment, the source and drain regions 402 and the source and drain regions 1102 are dissimilar. In this regard, in one embodiment, if the regions 402 are doped as p-type regions, the regions 1102 are doped as n-type regions. In an alternate embodiment, if the regions 402 are doped as n-type regions, the regions 1102 may be doped as p-type regions.

FIG. 12 illustrates the patterning of a masking layer 1202 over the source and drain regions 1102, the dummy gate stack 206 a, and the spacers 1002. The masking layer 1202 may be formed by, for example, a lithographic patterning and etching process. Following the patterning of the masking layer 1202, an etching process such as, for example, a chemical etching process, is performed that removes exposed portions of the second layer of spacer material 602 (of FIG. 11). The removal of the second layer of spacer material 602 exposes the oxide material 502. The etching process is selective to the oxide layer 502 such that the etching process does not substantially remove the oxide layer 502 material.

FIG. 13 illustrates the removal of the masking layer 1202 to expose the source and drain region 1102, the spacers 1002 and the dummy gate stack 206 a.

FIG. 14 illustrates the resultant structure following the deposition of an insulating layer 1402 such as, for example an oxide material layer. The insulating layer 1402 may be formed by, for example, a CVD process. The insulating layer 1402 is formed over the source and drain regions 1002, the dummy gate stack 206 a, the spacers 1002 and the oxide layer 502 that is over the dummy gate stack 206 b, the spacers 304, and the source and drain regions 402.

FIG. 15 illustrates the resultant structure after a planarizing process such as, for example, chemical mechanical polishing (CMP) has been performed, which removes a portion of the insulator layer 1402 and exposes the dummy gate stacks 206 a and 206 b (of FIG. 14). The dummy gate stacks 206 are removed, and gate stacks 1502 a and 1502 b are formed. The gate stacks 1502 include a dielectric layer 1504 and a gate electrode layer 1506. The finFET device 1500 a includes the gate stack 1502 a, the spacers 1002, and the source and drain regions (active regions) 1102. The finFET device 1500 b includes the gate stack 1502 b, the spacers 304 and the source and drain regions (active regions) 402. In one exemplary embodiment, the finFET device 1500 a is a pFET type device and the finFET device 1500 b is an nFET type device. In alternate exemplary embodiments, the finFET device 1500 a is an nFET type device and the finFET device 1500 b is a pFET type device. The finFET devices 1500 a and 1500 b have spacers 1002 and 304 that have substantially similar thicknesses (t) for the length of the spacer (i.e., from the top surface of the gate stacks 1502 to the top of the fins 204 a and 204 b.

The exemplary methods and structures described herein include finFET devices having different type active regions and spacers having substantially similar thicknesses, which improves the performance of the devices.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one more other features, integers, steps, operations, element components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

The diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.

While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described. 

1. A field effect transistor device comprising: a first semiconductor fin arranged on a substrate, the first semiconductor fin is doped with n-type dopants; a second semiconductor fin arranged on the substrate, the second semiconductor fin is doped with p-type dopants; a first gate stack arranged over the first semiconductor fin; a second gate stack arranged over the second semiconductor fin; a first spacer arranged adjacent to the first gate stack, the first spacer having a substantially uniform thickness; and a second spacer arranged adjacent to the second gate stack, the second spacer having a substantially uniform thickness, wherein the thickness of the first spacer is substantially similar to the thickness of the second spacer; wherein the first semiconductor fin includes a first epitaxially grown semiconductor material grown from a surface of the first semiconductor fin, the first epitaxially grown semiconductor material adjacent to at least a portion of sides of the first spacer; and wherein the second semiconductor fin includes a second epitaxially grown semiconductor material grown from a surface of the first semiconductor fin, the second epitaxially grown semiconductor material adjacent to at least a portion of sides of the second spacer.
 2. (canceled)
 3. The device of claim 1, wherein the first spacer contacts the first semiconductor fin and the first epitaxially grown semiconductor material grown from a surface of the first semiconductor fin.
 4. The device of claim 1, wherein the second spacer contacts the second semiconductor fin and the second epitaxially grown semiconductor material grown from a surface of the second semiconductor fin.
 5. The device of claim 1, wherein the first semiconductor fin includes silicon.
 6. The device of claim 1, wherein the first semiconductor fin includes silicon germanium.
 7. The device of claim 1, wherein the first spacer includes a nitride material.
 8. The device of claim 1, wherein the first spacer includes an oxide material.
 9. The device of claim 1, wherein the first gate stack is arranged over a channel region of the first semiconductor fin.
 10. The device of claim 1, wherein the second gate stack is arranged over a channel region of the second semiconductor fin.
 11. The device of claim 1, wherein the second semiconductor fin includes silicon.
 12. The device of claim 1, wherein the second semiconductor fin includes silicon germanium.
 13. The device of claim 1, wherein the first or second epitaxially grown semiconductor material includes silicon.
 14. The device of claim 1, wherein the first or second epitaxially grown semiconductor material includes silicon germanium.
 15. The device of claim 1, wherein the second spacer includes a nitride material.
 16. The device of claim 1, wherein the second spacer includes an oxide material.
 17. A field effect transistor device comprising: a first semiconductor fin arranged on a substrate; a second semiconductor fin arranged on the substrate; a first gate stack arranged over the first semiconductor fin; a second gate stack arranged over the second semiconductor fin; a first spacer arranged adjacent to the first gate stack, the first spacer having a substantially uniform thickness; and a second spacer arranged adjacent to the second gate stack, the second spacer having a substantially uniform thickness, wherein the thickness of the first spacer is substantially similar to the thickness of the second spacer; wherein the first semiconductor fin includes a first epitaxially grown semiconductor material grown from a surface of the first semiconductor fin, the first epitaxially grown semiconductor material adjacent to at least a portion of sides of the first spacer; and wherein the second semiconductor fin includes a second epitaxially grown semiconductor material grown from a surface of the first semiconductor fin, the second epitaxially grown semiconductor material adjacent to at least a portion of sides of the second spacer.
 18. The device of claim 17, wherein the first semiconductor fin is doped with n-type dopants.
 19. The device of claim 17, wherein the second semiconductor fin is doped with p-type dopants.
 20. (canceled) 